I am doing some research work on High Level System Design With System Ca and VHDL and Verilog. This is part of the research Work that I am doing for my Phd Thesis.
Some important discoveries and comments will be posted here.
In short I forund the Information useful form the following places.
1.0 Aldec Web Seminar on system C.
2.0 Mentor Graphics Papers on System C.
3.0 Technical Material from CMC Canada.
More on this will come later.
Subscribe to:
Post Comments (Atom)
No comments:
Post a Comment