VITAL Standard and System C Class Libraies

Are there any commonalities between System C class Libraries and VHDL/Verilog VITAL Libraries?

Any pointers on this topic will be Highly appreciated.

PCB Layout Programs

I am workig on PCB layout CAD tools called orcad and allegro.
IS there any books and tutorials that can speed up the process.
I have located some old information in Berkeley Tutorial.
any books and informaton will be useful.


I have also joined cadence Orcad discussion groups

High Level System Design with System C

I am doing some research work on High Level System Design With System Ca and VHDL and Verilog. This is part of the research Work that I am doing for my Phd Thesis.

Some important discoveries and comments will be posted here.

In short I forund the Information useful form the following places.

1.0 Aldec Web Seminar on system C.
2.0 Mentor Graphics Papers on System C.
3.0 Technical Material from CMC Canada.

More on this will come later.

Hervard Busine Communication Series

I am exploring Harverd business communication series and graduate courses on business communication from Sloan School of Management.

Such Courses are not providde in Canadian Emginmeering/MBA schools and I find them it is very important for Small Busines and For Keen Computter Operations.

As we dig though the materials ; I will post my finsdings.

ARM-7 Development suystems

We are working on ARM-& based edevelopment system.
In particular with IVR and KEIL SYstems.
More on this later.

Aldec VHDL Simulator

I am testing Aldec VHDL Simulator and Found the Tool to be extremely cost effective and useful. More on this later

Design of Embeded Telecommunications System

We are designing an embeded Telecommiunication Devuice based on linux kernel.

So far our Tools Include the following

1.0 NS2 Simulator

2.0 Enbeded Linux Kernel

3.0 Sokris Network Processor Boards

4.0 Sun Solaris-8 Based Workstation.

We are working on the test and complience strategy at this point.

VHDL- 93 and Foreign Language Interface

We are in Creating Vital complient VHDL Libraries. So far we have not come across any foeighn Laguage API Issues. Is there any working group that is working on that. I would love to summarize findings on the issues.